This invention relates to devices and methods for generating prioritized error-detection schedules for integrated circuits having memory, and more particularly, to adjusting the error checking frequency of memory based on adjustable region-specific criticality weights.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. Logic functions implemented on a programmable integrated circuit may be used to perform a variety of tasks that have varying degrees of criticality or importance to the overall functioning of the integrated circuit. It may be desirable to check memory regions used to configure critical logic functions more frequently than memory regions used to configure non-critical logic functions.
Configuration random access memory (CRAM) in the programmable integrated circuit are used to store configuration data to implement user logic functions. Logical values stored in the CRAM are used to configure circuits in the programmable integrated circuit that perform different functions within the device. These different functions may have respective levels of criticality. Consequently, the memory cells used to program these circuits may have different respective levels of criticality to the functioning of the programmable integrated circuit device.
Conventional programmable circuits scan CRAM cells for errors uniformly, checking each cell within the CRAM for errors with a common frequency or at a single rate. However, this error detection scheme may result in sub-optimal performance of the integrated circuit, as the circuitry used to implement critical logic functions (where errors are relatively less tolerable) is checked with the same frequency as circuitry used to implement non-critical logic functions (where errors are relatively more tolerable).
CRAM cells are susceptible to single event upsets (SEUs) that cause bit-flips in the CRAM cells. SEUs are sometimes referred to as “soft errors” because they are not permanent faults (or, “hard” errors) and can be reversed (by re-writing a correct value into the affected memory cell). When one or more CRAM cells experience bit-flips due to SEUs, the errors in the CRAM can become harder to detect and correct. Moreover, the longer a system takes to detect and correct a SEU, the likelihood of the error adversely affecting system operation or leading to faulty/erroneous operation of device resources increases. For this reason, it is desirable to perform error detection operations on regions of a CRAM array that configure critical circuitry frequently.
Conventional CRAM arrays undergo error detection in a uniform manner, with each CRAM cell being checked for errors at a common frequency. As an example, if a programmable integrated circuit has the ability to detect errors in a row of CRAM bits at a time, if it takes 100 nanoseconds (ns) to check each row, and if a CRAM array has 100,000 rows, then each bit in the CRAM array will be checked every 10 million ns or 10 milliseconds (ms) in a conventional arrangement. In certain applications, however, an error in CRAM cells that configure critical logic functions that persists for over 5 ms, 2 ms, or even 1 ms may result in unacceptable performance degradation or even failure.
Therefore, improved methods for providing error detection capabilities to integrated circuits with arrays of memory cells are required.